TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 10

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.1.2
Reset Operation
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input to low for at least 20 system clocks (16 μs at fc = 40
MHz).
program counter settings. CPU internal registers not mentioned above do not change when
the reset is released.
The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The
external RAM data provided before turning on the TMP92CM22 may be spoiled because the control signals are
unstable until power supply becomes stable after power on reset.
When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage
When the reset has been accepted, the CPU performs the following:
When the reset is released, the CPU starts executing instructions according to the
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
Figure 3.1.1 shows the timing of a reset for the TMP92CM22.
Internal reset is released as soon as external reset is released and
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Sets the stack pointer (XSP) to 00000000H.
Sets bits <IFF0:2> of the status register (SR) to 111 (Thereby setting the interrupt
Clears bits <RFP0:1> of the status register to 00 (Thereby selecting register bank
Initializes the internal I/O registers as “Table of Special Function Registers
Sets the input or output port to general-purpose input port.
Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
level mask register to level 7).
0).
(SFRs)” in Section 5.
PC<7:0>
PC<15:8>
PC<23:16> ← Data in location FFFF02H
← Data in location FFFF00H
← Data in location FFFF01H
92CM22-8
RESET
input pin is set to “H”.
TMP92CM22
2007-02-16