TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 194

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
SCK pin output
SO pin output
Writing
transmission
data
(1) Serial Clock
Figure 3.10.23 Maximum Data Transfer Frequency when External Clock Input
1.
Internal clock
External clock (<SCK2:0> = “111”)
Clock source
signal is output to the outside on the SCK pin.
cannot follow the serial clock rate, so an automatic wait function is executed
which automatically stops the serial clock and holds the next shift operation until
reading or writing has been completed.
ensure the integrity of shift operations, both the high and low-level serial clock
pulse widths shown below must be maintained. The maximum data transfer
frequency is 1.25 MHz (when f
SCK pin
SBI0CR1<SCK2:0> is used to select the following functions:
In internal clock mode one of seven frequencies can be selected. The serial clock
When the device is writing (in transmit mode) or reading (in receive mode), data
An external clock input via the SCK pin is used as the serial clock. In order to
a
Figure 3.10.22 Automatic Wait Function
a
1
0
t
SCKL and
a
2
1
t
SCKL
a
3
2
a
t
5
t
SCKH
SCKH
92CM22-192
a
7
6
> 8 f
a
8
Automatic wait
7
SYS
SYS
= 20 MHz).
b
b
1
0
b
c
2
1
b
4
b
6
5
b
7
6
b
8
7
c
1
0
c
2
1
c
TMP92CM22
3
2
2007-02-16

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