TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 92

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
3.6.4
CLKOUT
A0 to A23
D0 to D31
CS2
RD
ROM Control (Page mode)
mode is set by the page ROM control register.
(1) Operation and how to set the registers
(2) Signal pulse
Note: Set the number of waits (“n”) using the control register (BnCSL) in each block address
This section describes ROM page mode accessing and how to set registers. ROM page
mode is specified only in block address area 2.
<OPGE> of the PMEMCR register to “1” sets the memory access of the block address
area to ROM page mode access.
The TMP92CM22 supports ROM access of the page mode. ROM access of the page
ROM page mode is set by the page ROM control register (PMEMCR). Setting
The number of read cycles is set by the <OPWR1:0> bit of the PMEMCR register.
area.
The page size (The number of bytes) of ROM in the CPU side is set by the
<PR1:0> of the PMEMCR register. When data is read out up to the border of the
set page, the controller completes the page reading operation. The start data of
the next page is read in the normal cycle. The following data is set to page read
again.
Figure 3.6.2 Page mode access Timing (8-byte example)
OPWR1
PR1
0
0
1
1
0
0
1
1
t
CYC
OPWR1/OPWR0 Bit (PMEMCR register)
t
AD3
t
AD3
OPWR0
PR1/PR0 Bit (PMEMCR register)
+0
PR0
0
1
0
1
0
1
0
1
Data
input
92CM22-90
Number of Cycle in A Page
1 state (n-1-1-1 mode) (n ≥ 2)
2 states (n-2-2-2 mode) (n ≥ 3)
3states (n-3-3-3 mode) (n ≥ 4)
(Reserved)
ROM Page Size
64 bytes
32 bytes
16 bytes
8 bytes
t
HA
t
AD2
+1
Data
input
t
HA
t
AD2
+2
Data
input
t
HA
t
AD2
+3
Data
input
TMP92CM22
t
t
HA
HR
2007-02-16

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