TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 84

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(2) Connection memory specification
(3) Data bus width specification
memory type to be connected with the block address areas. The interface signal is
output according to the set memory as follows. TMP92CM22 prohibit changing default
(SRAM/ROM).
BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows.
called “dynamic bus sizing”. The part where the data is output to is depended on the
data size, the bus width and the start address.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories
Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the
The data bus width is set for every block address area. The bus size is set by the
This way of changing the data bus size depending on the address being accessed is
BnBUS1
BnOM1
0
0
1
1
0
0
1
1
with different bus width are put in consecutive addresses, do not execute an
access to placed on both memories with one command.
BnOM1, BnOM0 Bit (BnCSH register)
BnBUS Bit (BnCSH register)
BnBUS0
BnOM0
0
1
0
1
0
1
0
1
92CM22-82
8-bit bus mode (Default)
SRAM/ROM (Default)
16-bit bus mode
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Function
Function
TMP92CM22
2007-02-16