TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 59

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(0017H)
(0016H)
(0014H)
P5FC
P5CR
P5
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Note1: Read-modify-write instruction is prohibited for registers P5CR and P5FC.
Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output.
However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address
bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as
output port. Please be careful when using this setting.
P57C
P57F
P57
7
7
7
0
1
P56C
P56F
P56
6
6
6
0
1
Data from external port (Output latch register is cleared to “0”.)
Figure 3.5.6 Register for Port 5
Port 5 Function Register
Port 5 Control Register
P55C
P55F
P55
5
5
5
0
1
Port 5 Register
0: Port 1: Address bus (A8 to A15)
92CM22-57
0: Input 1: Output (Note2)
P54C
P54F
P54
4
4
4
0
1
R/W
W
W
P53C
P53F
P53
3
3
3
0
1
P52C
P52F
P52
2
2
2
0
1
P51C
P51F
P51
1
1
1
0
1
P50C
P50F
TMP92CM22
P50
0
0
0
0
1
2007-02-16