TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 18

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.3.3
(High-speed clock gear changing)
System Clock Controller
internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and
PLL (Clock doubler) SYSCR1<GEAR2:0>, SYSCR1<GEAR2:0> sets the high-frequency
clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce
the power consumption of the equipment in which the device is installed.
cause the system clock (f
and X2 pins.
(1) Clock gear controller
The system clock controller generates the system clock signal (f
Single clock mode is set by resetting, initialized to <GEAR2:0> = “100”. This setting will
For example, f
SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a
lower value of f
register. It is necessary the warm-up time until changing after writing the register
value.
instruction is executed by the clock gear before changing. To execute the instruction
next to the clock gear switching instruction by the clock gear after changing, input the
dummy instruction as follows (Instruction to execute the write cycle).
Example:
Changing to a high-frequency gear
SYSCR1
X: Don’t care
Example:
SYSCR1
f
To change the clock gear, write the register value to the SYSCR1<GEAR2:0>
There is the possibility that the instruction next to the clock gear changing
FPH
is set according to the contents of the clock gear select register
SYS
EQU
LD
EQU
LD
LD
FPH
is set to 1.25 MHz when the 40MHz oscillator is connected to the X1
reduces power consumption.
SYS
10E1H
(SYSCR1), XXXX0100B
10E1H
(SYSCR1), XXXX0001B
(DUMMY), 00H
Instruction to be executed
after clock gear has changed.
) to be set to fc/32 (fc/16×1/2).
92CM22-16
;
;
;
Changes system clock f
Changes f
Dummy instruction.
SYS
to fc/4.
SYS
) for the CPU core and
SYS
to fc/32.
TMP92CM22
2007-02-16