TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 38

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
DMAR
Name
request
DMA
(2) Soft start function
(3) Transfer control registers
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
bit, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the
DMAR register is automatically cleared to “0”.
one bit.)
writing 1. If read “1”, micro DMA transfer isn’t started yet.
the value in the micro DMA transfer counter is “0” after start up of the micro DMA. If
execatee soft start during micro DMA transfer by interrupt source, micro DMA
transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid
writign to other bits by mistake.
following registers. Data setting for these registers is done by an “LDC cr, r”
instruction.
Address
(Prohibit
RMW)
In addition to starting the micro DMA function by interrupts, TMP92CM22 includes
Writing “1” to each bit of DMAR register causes micro DMA once (If write “0” to each
Only one channel can be set for DMA request at once. (Do not write 1 to more than
When writing again 1 to the DMAR register, check whether the bit is 0 before
When a burst is specified by DMAB register, data is continuously transferred until
The transfer source address and the transfer destination address are set in the
109H
DREQ7
7
0
Channel 0
Channel 7
DMAS0
DMAD0
DMAS7
DMAD7
32 bits
DREQ6
6
0
DMAC0
DMAC7
16 bits
92CM22-36
DMAM0
DMAM7
8 bits
DREQ5
5
0
1: DMA request in software
DMA Source address register 0: only use LSB 24 bits.
DMA Destination address register 0: only use LSB 24 bits.
DMA Counter register 0: 1 to 65536.
DMA Mode register 0.
DMA Source address register 7.
DMA Destination address register 7.
DMA Counter register 7.
DMA Mode register 7.
DREQ4
4
0
R/W
DREQ3
3
0
DREQ2
2
0
DREQ1
1
TMP92CM22
0
2007-02-16
DREQ0
0
0