TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 15

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
3.3.1
X1
X2
Block Diagram of System Clock
frequency
oscillator
High-
Figure 3.3.2 Block Diagram of Dual Clock and System Clock
f
SYS
φT0
f
φT
iO
f
PLLCR<PLLON>
OSCH
(Clock doubler)
PLL
SYSCR2<WUPTM1:0>
PLLCR<PLUPFG>
Warm-up timer (for high-frequency
f
TMRA0 to TMRA3 and
TMRB0 to TMRB1
PLL
SIO0 and SIO1
oscillator)/lockup (for PLL) timer
SBI
Prescaler
Prescaler
Prescaler
= f
OSCH
PLLCR<FCSEL>
× 4
92CM22-13
fc
÷2
fc/2
Clock gear
÷4
fc/4
÷8
fc/8
fc/16
÷16
SYSCR1<GEAR2:0>
controller
Interrupt
I/O port
WDT
CPU
RAM
ADC
f
FPH
÷2
÷4
÷2
÷8
TMP92CM22
2007-02-16
f
f
φT
φT0
SYS
iO

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