TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 83

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Bit symbol
Setting value
Bit symbol
Setting value
(iii) Example of register setting
register as follows.
with address A23 to A16.
value specifies the start address of the block address area to address 110000H.
MAMR1 set whether address A21 to A16 and A8 are compared or not. Set the
register to “0” to compare, or to “1” not to compare. A23 and A22 are always
compared.
start addresses. Therefore 512 bytes of addresses 110000H to 1101FFH are set
as the block address area 1, and compared with the addresses on the bus. If the
compared result is a match, the chip select signal
to A15 are compared or not is set to register.
are processed as the CSEX space. Therefore, settings of CSEX apply for the
control of wait cycles, data bus width, etc.
To set the block address area 1 to 512 bytes from address 110000H, set the
M1S23 to M1S16 bits of the memory start address register MSAR1 correspond
A15 to A0 are cleared to “0”. Therefore setting MSAR1 to the above-mentioned
The start address is set as it is in the other block address areas.
M1V21 to M1V16 and M1V8 bits of the memory address mask register
Setting the above-mentioned compares A23 to A9 with the values set as the
The other block address area sizes are specified like this.
Similarly, A23 is always compared in block address areas 2 to 3. Whether A22
Note: When the set block address area overlaps with the built-in memory area,
Also that any accessed areas outside the address spaces set by
M1S23
M1V21
0
7
7
0
or both two address areas overlap, the block address area is processed
according to priority as follows.
Built-in I/O > Built-in memory > Block address area 0 >1 > 2 > 3 > CSEX
M1S22
M1V20
0
6
6
0
M1S21
M1V19
0
5
5
0
92CM22-81
MAMR1 Register
MSAR1 Register
M1S20
M1V18
1
4
4
0
M1S19
M1V17
0
3
0
3
M1S18
M1V16
2
0
0
2
CS1
M1V15-9
M1S17
is set to “low”.
0
1
1
0
M1S16
M1V8
1
0
0
1
TMP92CM22
CS0
2007-02-16
to
CS3