TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 244

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

TB0RG0H
TB0RG1H
TB0FFCR
TB0RG0L
TB0RG1L
TB0CP0H
TB0CP1H
TB0CP0L
TB0CP1L
Symbol
TB0MOD
TB0RUN
(7) 16-bit timer (1/2)
16-bit timer
16-bit timer
16-bit timer
16-bit timer
Timer B0
Timer B0
Timer B0
register 0
register 0
register 1
register 1
register 0
register 0
register 1
register 1
Capture
Capture
Capture
Capture
Name
register
register
register
flip-flop
control
mode
RUN
high
high
high
high
low
low
low
low
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
118AH
118BH
118CH
118DH
118EH
1180H
1182H
1183H
1188H
1189H
118FH
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
Always write “11”.
Double
buffer
0: Disable
1: Enable
Always
write “0”.
TB0RDE
7
0
−
0
1
−
R/W
R/W
W*
Always
write “0”.
Always
write “0”.
6
−
0
−
0
1
−
92CM22-242
Invert when
the UC10
value is
loaded in to
TB0CP1H/L.
0: Software
1: Undefined
Software
capture
control
TB0FF0 inversion trigger
0: Trigger disable
1: Trigger enable
TB0C1T1 TB0C0T1
TB0CP0I TB0CPM1 TB0CPM0
capture
W
5
1
0
Invert when
the UC10
value is
loaded in to
TB0CP0H/L.
Capture timing
00: Disable
01: Reserved
10: Reserved
11: TA1OUT↑
TA1OUT↓
4
0
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
R
R
R
R
−
−
−
−
−
−
−
−
Invert when
the UC10
matches with
TB0RG1H/L.
IDLE2
0: Stop
1: Operate
TB0E1T1
I2TB0
3
0
0
0
R/W
Invert when
the UC10
matches with
TB0RG0H/L.
0: Clear
1: Clear
TB0PRUN
TMRB0
prescaler
0: Stop and clear
1: Run (Count up)
Up counter
control
TB0E0T1
TB0CLE
disable
enable
R/W
2
0
0
0
* Always read as 11.
Timer B0 source clock
Control TB0FF0
00: Invert
01: Set
10: Clear
11: Don’t care
TB0CLK1 TB0CLK0
TB0FFC1 TB0FFC0
00: Reserved
01: φT1
10: φT4
11: φT16
1
0
1
TMP92CM22
2007-02-16
W*
UP counter
(UC10)
TB0RUN
R/W
0
0
0
1