TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 31

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.4
Interrupt
by the built-in interrupt controller.
to the CPU. If multiple interrupts is generated simultaneously, the interrupt controller sends
the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for
non-maskable interrupts.)
mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the
interrupt mask register, the CPU accepts the interrupt.
instruction (EI num sets <IFF2:0> data to num).
interrupt controller is 3 or higher, and also non-maskable interrupts.
instruction is used to disable maskable interrupts because of the priority level of maskable
interrupts is 1 to 6. The EI instruction is valid immediately after execution.
micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes)
automatically in micro DMA mode, therefore this mode is used for speed-up interrupt
processing, such as transferring data to the internal or external peripheral I/O. Moreover,
TMP92CM22 has software start function for micro DMA processing request by the software not
by the hardware interrupt.
Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and
The TMP92CM22 has a total of 41 interrupts divided into the following types:
A individual interrupt vector number (Fixed) is assigned to each interrupt.
One of six priority level (Variable) can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
The CPU compares the priority level of the interrupt with the value of the CPU interrupts
The interrupt mask register <IFF2:0> value can be updated using the value of the EI
For example, specifying “EI3” enables the maskable interrupts which priority level set in the
Operationally, the DI instruction (<IFF2:0> = 7) is identical to the EI7 instruction. DI
In addition to the above general-purpose interrupt processing mode, TLCS-900/H1 has a
Figure 3.4.1 shows the overall interrupt processing flow.
Interrupts generated by CPU: 9 sources
External interrupts (
Internal I/O interrupts: 17 sources
High-speed DMA interrupts: 8 sources
(Software interrupts: 8 sources, illegal instruction interrupt: 1 source)
NMI
and INT0 to INT5): 7 sources
92CM22-29
TMP92CM22
2007-02-16