TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 214

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.12.2
WDT counter
WDT interrupt
WDT clear
(Software)
WDT counter
WDT interrupt
Internal reset
Operation
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
reset.
continues counting during bus release (when
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
the input clock. The binary counter can output 2
In this case, the reset time will be between 22 and 29 system clocks (35.2 to 46.4 μs at
f
f
clock gear function
OSCH
FPH
The watchdog timer generates an INTWD interrupt when the detection time set in the
The watchdog timer begins operating immediately on release of the watchdog timer
The watchdog timer is halted in IDLE1 or STOP mode. The watchdog timer counter
When the device is in IDLE2 mode, the operation of WDT depends on the
The watchdog timer consists of a 22-stage binary counter which uses the clock φ (2/f
The runaway detection result can also be connected to the reset pin internally.
is generated by dividing the high-speed oscillator clock (f
= 40 MHz) as shown inFigure 3.12.3. After a reset, the f
n
n
Figure 3.12.2 Normal Mode
Figure 3.12.3 Reset Mode
Overflow
22 to 29 clocks (35.2 to 46.4 μs at f
92CM22-212
Overflow
BUSAK
15
/f
IO
, 2
Write clear code
goes low).
17
OSCH
/f
IO
, 2
OSCH
= 40 MHz)
19
SYS
/f
IO
) by sixteen through the
clock is f
and 2
21
/f
TMP92CM22
FPH
IO
2007-02-16
.
0
/2, where
IO
) as