TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 84
TMPM370FYFG
Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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<bit28:7>
<bit29>
7.6.2.18
<TBLOFF>
<TBLBASE> The vector table is in:
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Vector Table Offset Register
Offset value
TBLOFF
0 = Code space
1 = SRAM space
Set the offset value from the top of the space specified in TBLBASE.
The offset must be aligned based on the number of exceptions in the table. This
means that the minimum alignment is 32 words that you can use for up to 16
interrupts. For more interrupts, it is necessary to adjust the alignment by rounding
up to the next power of two.
R/W
15
23
31
7
0
“0” is read.
R
0
14
22
30
6
TMPM370 7-46
Table base
TBLBA
R/W
SE
29
13
21
5
0
28
12
20
4
Offset value
Offset value
TBLOFF
TBLOFF
R/W
R/W
0
0
“0” is read.
19
27
11
3
R
0
Offset value
TBLOFF
R/W
10
18
26
2
0
17
25
9
1
TMPM370
Interrupt
16
24
0
8
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