TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 36

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

6.6.5
Release
source
● Release by interrupt request
● Release by Non-Maskable Ininterrupt (NMI)
● Release by reset
source that can be used is determined by the low power consumption mode selected. Details are
shown in Table 6-6.
detect the interrupt. In addition to the setting in the CPU, the clock generator must be set to detect
the interrupt to be used to release the STOP modes.
only be used in the IDLE mode.
mode switches to NORMAL and all the registers are initialized as is the case with normal reset.
reset signal valid until the oscillator operation becomes stable.
(Note 1)
(Note 2)
The low power consumption mode can be released by an interrupt request or reset. The release
To release the low power consumption mode by an interrupt, the CPU must be set in advance to
There is a watchdog timer interrupt (INTWDT) as a non-maskable interrupt source. INTWDT can
Any low power consumption modes can be released by reset from the R E S E T
Note that returning to NORMAL mode by reset does not induce the automatic warm-up. Keep the
Refer to “Interrupts" for details.
Releasing the Low Power Consumption Mode
NMI (INTWDT)
RESET (RESET pin)
Interrupt
○:
×:
Starts the interrupt handling after the mode is released. (The reset
initializes the LSI).
Unavailable
INT0 to INTF (Note 1)
INTRX0 to 3, INTTX0 to 3
INTVCNA, INTVCNB
INTEMG0 to 1
INTOVV0 to 1
INTTB0 to 7
INTPMD0 to 1
INTENC0 to 1
INTCAP00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51, 60, 61, 70, 71
INTAD0PDA, INTAD1PDA, INTAD0PDB, INTAD1PDB
INTAD0CPA, INTAD1CPA, INTAD0CPB, INTAD1CPB
INTAD0SFT, INTAD1SFT
INTAD0TMR, INTAD1TMR
For shifting to the low power consumption mode, set the CPU to prohibit all the
interrupts other than the release source. If not, releasing may be executed by an
unspecified interrupt.
To release the low power consumption mode by using the level mode interrupt,
keep the level until the interrupt handling is started. Changing the level before
then will prevent the interrupt handling from starting properly.
Low power consumption mode
Table 6-6 Release Source in Each Mode
TMPM370 6-16
------------------------------
IDLE
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Clock/Mode control
pin. After that, the
STOP
○
×
×
×
×
×
×
×
×
×
×
×
×
×
○
TMPM370