TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 196

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TX Interrupts
(Note)
Double Buffer
Configuration
Single Buffer
Buffer
Table 10-5 Receive Interrupt conditions in use of FIFO
Fig. 10-11 shows the data flow of transmit operation and the route of write.
Single Buffer / Double Buffer
TX interrupts are generated at the time depends on the transfer mode and the buffer
configurations, which are given as follows.
FIFO
In use of FIFO, transmit interrupt is generated on the condition that the following either
operation and SC0TFC<TFIS> setting are established.
SC0RFC<RFIS>
Fig. 10-11 Transmit Buffer/FIFO Configuration Diagram
Transmittion completion of all bits of one frame.
If double buffer is enabled, a interrupt is also generated when the data is
moved from the buffer to the shift register by writing to the buffer.
“0”
“1”
When a data is moved from the transmit buffet to the transmit shift register.
Just before the stop bit is sent
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is greater than or equal to "the fill level of FIFO intrruption
generation."
UART mode
TMPM370 10-25
Immediately after the raising / falling edge of the last SCLK
(Rising
SC0CR<SCLKS> setting.)
Interrupt conditions
or
falling
IO interface modes
is
determined
Serial Channel
according
TMPM370
to