TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 26

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

<Bit 0><PLLSEL> : Specifies use or disuse of the clock multiplied by the PLL.
6.2.2.4
Read/Write
Read/Write
Read/Write
Read/Write
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Function
Function
Function
Function
Note: When the PLLSEL is controlled, the oscillation frequency detector (OFD) must
PLL Selection Register (CGPLLSEL)
“fosc” is automatically set after reset. Resetting is required when using the PLL.
Example of PLL setting
OFDCR1<OFDWEN7:0>=”0xF9”
OFDCR2<OFDEN7:0>=”0x00”
CGPLLSEL<PLLSEL>=”1”
OFDMNPLLON=”xxxx”
OFDMXPLLON=”yyyy”
OFDCR2<OFDEN7:0>=”0xE4”
OFDCR1<OFDWEN7:0>=”0x06”
be disablded beforehand even though the PLLSEL is controlled in an initial
routine. Note that the OFD reset doesn’t initialize OFD setting.
23
31
15
0
0
-
-
7
0
1
-
-
22
30
14
0
0
6
-
-
0
0
-
-
Write “1010”
R/W
TMPM370 6-6
13
21
29
5
1
1
-
-
0
0
-
-
Write “0011111”
:Write enable code for OFD registers
:OFD disable
:Enabling of PLL
:Lower detection frequency setting
:Higher detection frequency setting
:OFD enable
:Write disable code for OFD registes
R/W
12
20
27
4
1
0
-
-
0
0
-
-
“0” is read
“0” is read
R
R
“0” is read.
11
19
26
R
3
1
0
0
0
-
-
-
-
R/W
10
18
25
2
1
0
-
-
0
0
-
-
Clock/Mode control
Write “001”
R/W
17
24
1
1
9
0
-
-
0
0
-
-
TMPM370
Select PLL
output
0: fosc
1: fpll
PLLSEL
R/W
R/W
16
23
0
0
8
1
0
0
-
-
-