TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 167

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TMPM370FYFG

Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
The block diagram of this mode is shown below.
X; Don’t care −; no change
TB0RG0-WR
TB0EN
TB0RUN
TB0RG0
TB0RG1
TB0CR
TB0FFCR
TB0MOD
PACR
PAFR1
TB0RUN
TB0IN0
φT16
TB0CR<TB0WBF>
φT1
φT4
Each register in the 16-bit PPG output mode must be programmed as listed below.
← X
← X
Selector
Selector
7
1
1
0
*
*
*
*
*
X
X
X
6
0
0
*
*
*
*
*
Fig. 9-4 Block Diagram of 16-bit PPG Mode
X
X
X
5
0
1
*
*
*
*
*
X
X
4
0
0
0
*
*
*
*
*
16-bit comparator
Register buffer 0
(** = 01, 10, 11)
X
X
3
0
1
0
*
*
*
*
*
TB0RG0
X
2
0
1
1
1
0
*
*
*
*
TMPM370 9-24
X
X
1
X
0
1
1
1
*
*
*
*
*
16-bit up-counter UC0
X
0
0
0
0
1
*
*
*
*
*
Match
Internal data bus
Starts the TMRB0 module.
Stops the TMRB0
Specifies a duty. (16 bits
Specifies a cycle. (16 bits *32-bits register length)
Enables the TB0RG0 double buffering.
(Changes the duty/cycle when the INTTB0 interrupt is
generated)
Specifies to trigger TB0FF0 to reverse
when a match with TB0RG0 or TB0RG1 is detected,
and sets the initial value of TB0FF0 to "0."
Designates the prescaler output clock as the input clock,
and disables the capture function.
Assigns PA1 to output and TB0OUT
Starts TMRB0
TB0RUN<TB0RUN>
16-bit comparator
Register buffer 1
TB0RG1
Clear
16-bit Timer/Event Counters
TB0OUT (PPG output)
(TB0FF0)
*32-bits register length)
F/F
TMPM370

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