TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 28

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

6.3
6.3.1
6.3.2
Fig.6-1 shows the clock system diagram. Each clock is defined as follows.
The high-speed clock gear (fgear) and the prescaler clock ΦT0 are dividable.
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Reset initializes the clock configuration as follows.
Reset causes all the clock configurations to be the same as fosc.
Clock Control
fosc
fpll
fc
fgear
fsys
fperiph : Clock specified by CGSYSCR<FPSEL>
ΦT0
High-speed clock gear : fc, fc/2, fc/4, fc/8, fc/16
Prescaler clock : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16,fperiph/32
High-speed oscillator
PLL (phase locked loop circuit)
High-speed clock gear
Clock System Block Diagram
Initial Values after Reset
: Clock input from high-speed oscillator (X1 and X2)
: Clock octupled by PLL
: Clock specified by CGPLLSEL<PLLSEL> (high-speed clock)
: Clock specified by CGSYSCR<GEAR2:0>
: The same clock as fgear (system clock)
: Clock specified by CGSYSCR<PRCK2:0> (prescaler clock)
fc = fosc
fsys = fc (=fosc)
fperiph = fc (=fosc)
ΦT0 = fperiph (=fosc)
TMPM370 6-8
: ON (oscillating)
: OFF (stop)
: fc (no frequency dividing)
Clock/Mode control
TMPM370