TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 307

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

16.3.4.5 OVV Protection Control Circuit
16.3.4.6 OVV Control Register (PMDnOVVCR)
unit. This circuit is activated when the OVV input port is asserted.
protection circuit fixes the six port output lines in the conduction control circuit to high or low. At this time,
an OVV interrupt (INTOV) is generated. It is possible to turn off only the upper or lower phases or all
phases.
OVVSTA<OVVST> indicates that the OVV protection circuit is active.
protection is automatically released after the OVV protection circuit completes its operation.
input can be checked by reading OVVSTA<OVVI>.
matches the MDPRD value). (When 0.5 PWM period is selected, the release timing is when the PWM
counter equals 1 or MDPRD.)
then clear OVVCR<OVVEN> to 0. (These three instructions must be executed consecutively.)
the EMGREL register to prevent it from being inadvertently disabled.
<OVVEN>: OVV protection circuit enable/disable
<OVVRS>: OVV protection release
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
The OVV protection control circuit consists of an OVV protection control unit and a port output disable
The release of the OVV protection state is enabled by setting OVVCR<OVVEN> to 1. Then, OVV
The OVV protection state is released in synchronization with the PWM period (when the PWM count
To disable the OVV protection function, write 0x5A and 0xA5 in this order to the EMGREL register and
The OVV protection circuit can be disabled only after the specified key codes (0x5A, 0xA5) are written in
After reset
After reset
After reset
After reset
When the OVV input is asserted (H → L) for a specified period (set in OVVCR<OVVCNT>), the OVV
OVV protection is set through the OVV Control Register (OVVCR). A read value of 1 in
circuit is disabled.
(These three instructions must be executed consecutively.)
transition. After the overvoltage detection signal returns high, the OVV protection state can be
automatically released by a match between the PWM counter and the MDPRD register by setting this bit
to 1.
* The OVV protection state is not released while the OVV protection input is low. The state of this port
The OVV protection circuit is enabled by setting this bit to 1. In the initial state, the OVV protection
To disable this circuit, write 5A and A5 in this order to the EMGREL register and then clear this bit to 0.
The OVV protection state is entered when the overvoltage detection signal makes a high-to-low
0: Disable
1: Enable
0: Disable automatic release of OVV protection
1: Disable automatic release of OVV protection
* When 0.5 PWM period is selected (MDCR<INTPRD>=00), the OVV protection state is released
when the PWM counter equals 1 or MDPRD.
R → 0
R → 0
R → 0
R → 0
(PMD0:0x4005 043C, PMD1:0x4005 04BC)
31
23
15
0
0
0
7
0
-
-
-
-
ADIN1EN
R → 0
R → 0
R → 0
R/W
30
22
14
0
0
0
6
0
-
-
-
ADIN0EN
R → 0
R → 0
R → 0
R/W
29
21
13
0
0
0
5
0
-
-
-
TMPM370 16-23
(OVV)
R → 0
R → 0
R → 0
28
20
12
0
0
0
4
0
-
-
-
OVVMD
R/W
R → 0
R → 0
27
19
11
0
0
0
3
0
-
-
OVVISEL
R → 0
R → 0
R/W
26
18
10
0
0
0
2
0
-
-
OVVCNT
R/W
Motor control circuit
OVVRS
R → 0
R → 0
R/W
25
17
0
0
9
0
1
0
-
-
OVVEN
R → 0
R → 0
TMPM370
R/W
24
16
0
0
8
0
0
0
-
-