TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 294

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

16.3.2.1 PMD Control Register (PMDnMDCR)
<PWMMD>: PWM carrier waveform
<INTPRD>: PWM interrupt period
<PINT>: PWM interrupt timing
<DTYMD>: Duty mode
<SYNTMD>: Port output mode
<PWMCK>: PWM period extension mode
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
center-aligned PWM.
and four PWM periods.
register (MDPRD) are updated into their respective buffers when the internal counter equals 1 or the
MDPRD value.
maximum value. When the edge-aligned PWM mode is selected, an interrupt request is generated
when the PWM counter equals the MDPRD value. When the PWM interrupt period is set to every 0.5
PWM period, an interrupt request is generated when the PWM counter equals 1 or MDPRD.)
register for all three phases.
This bit selects the PWM mode. PWM mode 0 is edge-aligned PWM and PWM mode 1 is
This field selects the PWM interrupt period from 0.5 PWM period, one PWM period, two PWM periods
This bit selects whether to generate an interrupt request when the PWM counter equals its minimum or
When <INTPRD>=00, the contents of the compare registers (CMPU, CMPV, CMPW) and period
This bit selects whether to make duty setting independently for each phase or to use the CMPU
This bit specifies the port output setting of the U, V and W phases. (See Table 16-4.)
When <PWMCK>=0, the PWM counter operates with a resolution of 12.5 ns at fsys=80 MHz.
When <PWMCK>=1, the PWM counter operates with a resolution of 50 ns at fsys=80 MHz.
0: PWM mode 0 (edge-aligned PWM, sawtooth wave)
1: PWM mode 1(center-aligned PWM, triangular wave)
00: Interrupt request at every 0.5 PWM period (PWM mode 1 only)
01: Interrupt request at every PWM period
10: Interrupt request at every 2 PWM periods
11: Interrupt request at every 4 PWM periods
0: Interrupt request when PWM counter = 1
1: Interrupt request when PWM counter = MDPRD
0: 3-phase common mode
1: 3-phase independent mode
0: Normal period
1: 4x period
R→0
R→0
R→0
R→0
(PMD0:0x4005 0408, PMD1:0x4005 0488)
* Sawtooth wave: 12.5 ns, triangular wave: 25 ns
* Sawtooth wave: 50 ns, triangular wave: 100 ns
31
23
15
0
0
0
7
0
-
-
-
-
PWMCK
R→0
R→0
R→0
30
22
14
0
0
0
6
0
-
-
-
SYNTMD
R→0
R→0
R→0
29
21
13
0
0
0
5
0
-
-
-
TMPM370 16-10
DTYMD
R→0
R→0
R→0
28
20
12
0
0
0
4
0
-
-
-
R→0
R→0
R→0
PINT
R/W
27
19
11
0
0
0
3
0
-
-
-
R→0
R→0
R→0
26
18
10
0
0
0
2
0
-
-
-
INTPRD
Motor control circuit
R→0
R→0
R→0
25
17
0
0
9
0
1
0
-
-
-
PWMMD
R→0
R→0
R→0
TMPM370
24
16
0
0
8
0
0
0
-
-
-