TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 58

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

（７）Enabling interrupt by CPU
to the interrupt to be used to the CGICRCG register. See “7.6.3.5 CGICRCG (CG Interrupt Clear
Register)” for each value.
not used for exiting a standby mode. However, an “H” pulse or “H”–level signal must be input so
that the CPU can detect it as an interrupt request. Also, be aware of the description of “7.5.1.4
Precautions when using external interrupt pins”.
interrupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single
interrupt source.
interrupt. Writing “1” to the corresponding bit of the Interrupt Set-Enable Register enables the
intended interrupt.
are lost if pending interrupts are cleared. Thus, this operation is not necessary.
Interrupt requests from external pins can be used without setting the clock generator if they are
Enable the interrupt by the CPU as shown below.
Clear the suspended interrupt in the Interrupt Clear-Pending register. Enable the intended
Writing “1” to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended
To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts
At the end, PRIMASK register is zero cleared.
(Note)
(Note1)
(Note2)
●Clock generator register
CGIMCGn<EMCGm>
CGICRCG<ICRCG4-0>
CGIMCGn<INTmEN>
●NVIC register
Interrupt Clear-Pending<m>
Interrupt Set-Enable<m>
●Interrupt mask register
PRIMASK
n: register number
m: number assigned to each interrupt factor
m: corresponding bit
PRIMASK register cannot be modified by the user access level.
TMPM370 7-20
←
←
←
←
←
←
Active level
Value corresponding to the interrupt to be used
“1” (interrupt enabled)
“1”
“1”
“0”
TMPM370
Interrupt