TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 44

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TMPM370FYFG

Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
(1) Stacking
(2) Fetching an ISR
7.1.2.2
interrupt service routine. This is called “pre-emption”.
in the following order:
state of the stack after the register contents have been pushed.
table is located at address 0x0000_0000 in the code space. By setting the Vector Table Offset Register,
you can place the vector table at any address in the code or SRAM space.
When an exception occurs, the CPU suspends the currently executing process and branches to the
When the CPU detects an exception, it pushes the contents of the following eight registers to the stack
The SP is decremented by eight words by the completion of the stack push. The following shows the
The CPU enables instruction to fetch the interrupt processing with data store to the register.
Prepare a vector table containing the top addresses of ISRs for each exception. After reset, the vector
The vector table should also contain the initial value of the main stack.
(Pre-emption)
Exception
・Program Counter (PC)
・ Program Status Register (xPSR)
・ r0 - r3
・ r12
・ Link Register (LR)
Old SP
SP
Handling
<previous>
xPSR
and
TMPM370 7-6
r12
PC
LR
r3
r2
r1
r0
Branch
to
the
Interrupt
Service
TMPM370
Interrupt
Routine

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