TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 271

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(0x4005_0098)
(0x4005_0130)
VETRGCRC0
VETRGCRC1
(0x4005_01AC)
(0x4005_018C)
(0x4005_01B0)
VETRGCMP00
VETRGCMP01
VETRGCMP10
(0x4005_0190)
VETRGCMP11
15.4.3.22
15.4.3.23
<TRGCRC>: Used to correct the synchronizing trigger timing. The value to be set is:
* These registers are effective when one of the following PMD trigger modes is selected:
<VTRGCMP0> PMD setting: Specifies the trigger timing for sampling ADC in synchronization with
PMD.
<VTRGCMP1> PMD setting: Specifies the trigger timing for sampling ADC in synchronization with
PMD.
* These registers are ineffective when the PMD trigger output mode is set to trigger select output
The upper and lower register names correspond to channel 0 and channel 1 respectively.
The upper and lower register names correspond to channel 0 and channel 1 respectively.
(TRGOUT=1).
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
Read/Write
Read/Write
Read/Write
Read/Write
Function
Function
bit Symbol
bit Symbol
bit Symbol
bit Symbol
count-down match, count-up match, count-up/-down match
After reset
After reset
After reset
After reset
Function
Function
Function
Function
VETRGCRC Register
VETRGCMP Register
Correction time [s] ÷ PWM counter clock frequency [s]
31
15
31
15
31
15
TMPM370 15-30
0x0001 to (MDPRD value -1): Trigger timing
0x0001 to (MDPRD value-1): Trigger timing
MDPRD value to 0xFFFF: Prohibited
MDPRD value to 0xFFFF: Prohibited
Trigger timing setting
Trigger timing setting
・・・
・・・
・・・
・・・
・・・
・・・
0x0000: Prohibited
0x0000:Prohibited
Trigger correction
VTRGCMP0
VTRGCMP1
TRGCRC
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
－
－
－
R
R
R
Vector Engine (VE)
17
17
17
1
1
1
TMPM370
16
16
16
0
0
0