TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 33

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TMPM370FYFG

Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
6.5
6.6
6.5.1
(Note 1)
(Note 2)
consumption mode, specify the mode in the system control register CGSTBYCR<STBY2:0> and
execute the WFI (Wait For Interrupt) instruction. In this case, execute reset or generate the interrupt to
release the mode. Releasing by the interrupt requires settings in advance. See chapter 6 for details.
As an operation mode, NORMAL is available. The features of NORMAL mode are described below.
The TMPM370 has two low power consumption modes: IDLE and STOP. To shift to the low power
The features of each mode are described as follows.
Operation Modes
Low Power Consumption Modes
This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock.
It is shifted to the NORMAL mode after reset.
NORMAL Mode
Transition to the low power consumption mode by executing the WFE (Wait For
Event) instruction is prohibited as the TMPM370 does not offer any event for
releasing the low power consumption mode.
The TMPM370 does not support the low power consumption mode configured with
the SLEEPDEEP bit in the Cortex-M3 core. Setting the SLEEPDEEP bit of the system
control register is prohibited.
TMPM370 6-13
Clock/Mode control
TMPM370

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