TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 440

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

4) Automatic programming of protection bits (for each block)
(Note) Software reset is ineffective in the seventh bus write cycle of the automatic
This device is implemented with protection bits. This protection can be set for each block.
See Table 20-20 for table of protection bit addresses. This device assigns 1 bit to 1 block as
a protection bit. The applicable protection bit is specified by PBA in the seventh bus write
cycle. By automatically programming the protection bits, write and/or erase functions can be
inhibited (for protection) individually for each block. The protection status of each block can
be checked by the FCFLCS <BLPRO> register to be described later. This status of the
automatic programming operation to set protection bits can be checked by monitoring
FCFLCS <RDY/BSY> (See Table 20-15). Any new command sequence is not accepted
while automatic programming is in progress to program the protection bits. If it is desired to
stop the programming operation, use the hardware reset function. In this case, it is
necessary to perform the programming operation again because the protection bits may not
have been correctly programmed. If all the protection bits have been programmed, all the
FCFLCS <BLPRO> bits are set to "1" indicating that it is in the protected state (See Table
20-15). This disables subsequent writing and erasing of all blocks.
it is desired to stop operation, use the hardware reset function. In this case, it is necessary
to perform the automatic block erase operation again because the data erasing operation
has not been normally terminated.
Also, any protected blocks cannot be erased. If an automatic block erase operation has
failed, the flash memory is locked in the mode and will not return to the read mode. In this
case, execute hardware reset to reset the device.
protection bit programming command. The FLCS <RDY/BSY> bit turns to
"0" after entering the seventh bus write cycle.
TMPM370 20-48
Flash Memory Operation
TMPM370