TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 252

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(0x4005_001C)
(0x4005_0018)
VEERRINTEN
VECOMPEND
15.4.1.7
15.4.1.8
<VERRENA> Enables or disables the error detection interrupt in channel 0.
<VERRENB> Enables or disables the error detection interrupt in channel 1.
<VCENDA> Forcefully terminates the currently executing schedule in channel 0.
<VCENDB> Forcefully terminates the currently executing schedule in channel 1.
* When “1” is written to these bits, it is cleared in the next cycle. These bits always read as "0”.
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
Function
Function
Function
Function
VEERRINTEN Register
VECOMPEND Register
31
31
7
7
・・・
・・・
000000
000000
TMPM370 15-11
－
－
R
R
3
3
・・・
・・・
2
2
0x000000
0x000000
－
－
R
R
Channel 1 error
interrupt enable
Channel 1 forced
termination
0: －
1: Terminate
0: Disable
1: Enable
VERRENB
VCENDB
R/W
W
1
0
1
0
Channel 0 error
interrupt enable
Channel 0 forced
termination
0:
1: Terminate
0: Disable
1: Enable
Vector Engine (VE)
9
9
VERRENA
VCENDA
R/W
W
0
0
0
0
TMPM370
8
8