TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 148
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TMPM370FYFG
Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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TBnEN
(0x4001_0xx0)
9.4.1.1
<TBnEN>: Specifies the TMRBn operation. When the operation is disabled, no clock is supplied to the
Read/Write
Read/Write
Read/Write
bit Symbol
Read/Write
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
TMRBn enable register (channels 0 through 7)
other registers in the TMRBn module. This can reduce power consumption. (This disables
reading from and writing to the other registers.)
To use the TMRBn, enable the TMRBn operation (set to “1”) before programming each register
in the TMRBn module.
After the TMRBn operation is executed and then disabled, the settings will be maintained in
each registers.
0: Disabled
1: Enabled
operation
TMRBn
TBnEN
R/W
31
23
15
R
R
R
7
0
0
0
0
30
22
14
R
R
R
6
0
0
0
TMRBn enable register (n=0 to 7)
21
13
29
R
R
R
5
0
0
0
TMPM370 9-5
28
20
12
R
R
R
4
0
0
0
“0” is read.
27
19
11
R
R
R
R
3
0
0
0
0
26
18
10
R
R
R
2
0
0
0
16-bit Timer/Event Counters
25
17
R
R
9
R
1
0
0
0
24
16
R
R
8
R
0
0
0
0
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