TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 151

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TBnMOD
(0x4001_0xxC)
9.4.1.4
＜TBnCLK1:0＞:Selects the TMRBn timer count clock.
＜TBnCLE＞:Clears and controls the TMRBn up-counter.
＜TBnCPM1:0＞:Specifies TMRBn capture timing.
＜TBnCP0＞:Captures count values by software and takes them into capture register 0 (TBnCP0).
Read/Write
After reset
Read/Write
Read/Write
Read/Write
bit Symbol
bit Symbol
bit Symbol
bit Symbol
After reset
After reset
After reset
Function
TMRB mode register (channels 0 thorough 7)
00: select TBnIN input pin
00: software capture
01: select φT1
01: Don’t care
11: select φT16 (1/32φT0)
10: select φT4
0: Disables clearing of the up-counter.
1: Clears up-counter if there is a match with timer register 1 (TBnRG1).
00: Capture disable
01: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN pin input.
10: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN pin input.
11: .Capture disable
“0”
is read.
31
23
15
R
R
R
7
R
0
0
0
0
Takes count values into capture register 1 (TBnCP1) upon falling of TBnIN pin input.
Writes to
0 and 1
(when
1: Must be
TBnRSWR
timer
registers
double
buffering is
enabled)
written
separately
written
simultaneo
usly
0: Can be
R/W
30
22
14
R
R
R
6
0
0
0
0
(1/8φT0)
(1/2φT0)
TMRBn mode register(n=0 to 7)
Software
capture
control
0: Software
capture
1: Don't
care
TBnCP0
29
21
13
W
R
R
R
5
0
0
0
1
TMPM370 9-8
00: Disable
01: TBnIN ↑
10: TBnIN ↑ TBnIN ↓
11: Disable
Capture timing
TBnCPM1 TBnCPM0
28
20
12
R
R
R
4
0
0
0
0
27
19
11
R
R
R
3
0
0
0
0
clear control
0:
Clear/disable
1:
clear/enable
Up-counter
TBnCLE
R/W
26
18
10
R
R
R
2
0
0
0
0
16-bit Timer/Event Counters
00: TBnIN pin input
01: φT1
10: φT4
11: φT16
TBnCLK1
Source clock select
25
17
R
R
9
R
1
0
0
0
0
TBnCLK0
24
16
R
R
R
8
0
0
0
0
0
TMPM370