TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 421

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 19th to 25th bytes must result in 00H (with the carry
dropped). If it is not 00H, one or more bytes of data has been corrupted. In case of a
checksum error, the RAM Transfer routine sends back 0x11 to the controller and
returns to the state in which it waits for a command (i.e., the 3rd byte) again.
TMPM370FY. Storage begins at the address specified by the 19th–22nd bytes and
continues for the number of bytes specified by the 23rd–24th bytes.
• The RAM storage start address must be within the range of 0x2000_0400 to the
When the above checks have been successful, the RAM Transfer routine returns a
normal acknowledge response (0x10) to the controller.
end address of RAM.
TMPM370 20-29
Flash Memory Operation
TMPM370