TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 29

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

6.3.3
6.3.4
(Note)
The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up
function.
from the low power consumption mode triggers the automatic timer count. After the specified time is
reached, the system clock is output and the CPU starts operation.
consideration of the stability time of the PLL.
lowers the oscillator input frequency while increasing the internal clock speed.
This circuit outputs the fpll clock that is octuple of the high-speed oscillator output clock, fosc. This
The PLL is disabled after reset is released. To enable the PLL, set "1" to the CGOSCCR<PLLON> bit.
The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer.
The warm-up function is used when returning from STOP mode. In this case, an interrupt for returning
In STOP modes, the PLL is disabled. When returning from these modes, configure the warm-up time in
(Note)
CGOSCCR<XEN1>
oscillator
Clock Multiplication Circuit (PLL)
Warm-up Function
It takes approx. 200μs for the PLL to be stabilized.
External
The input clocks to selector shown with an arrow are set as default after reset.
fosc
CGOSCCR<PLLON>
CGPLLSEL<PLLSEL>
PLL
fosc
fpll
OFD monitoring clock
A/D conversion clock
Fig.6-1 Clock Block Diagram
CGOSCCR<WUEON>
CGOSCCR<WUODR>
fc
Warm-up timer
TMPM370 6-9
1/2 1/4 1/8 1/16
CGSYSCR<GEAR2:0>
CGSYSCR<FPSEL>
TMRB, WDT,VE,PMD
ENC,VLTD,CMP,AMP
SIO,ADC,PORT,OFD
CPU, ROM, RAM,
[AHB-Bus I/O]
BOOT ROM
[IO-Bus I/O]
fgear
fsys
fperiph
1/2 1/4 1/8 1/16 1/32
[Peripheral I/O, prescaler input]
Clock/Mode control
CGSYSCR<PRCK2:0>
TMRB,SIO
TMPM370
ΦT0