TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 391

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

according to the selected operating mode.
19.3.5 Counter Block
The counter is configured as an up-counter or a down-counter, cleared and reloaded with a programmed value,
19.3.5.1 Overview
The counter block consists of a 24-bit up/down counter and its control logic.
Table 19.4 Counter Control
Sensor Event Count
Sensor Timer Count
Operating Mode
Note: Clearing <ENRUN> to 0 does not clear the counter.
Encoder Mode
<MODE1:0>
Timer Mode
Setting <ENRUN> to 1 again causes the counter to restart from the current count.
The counter should be cleared by software setting <ENCLR> to 1.
Mode
Mode
00
01
10
11
Table 19.4 summarizes how the counter is controlled.
0
1
0
0
0
1
X
0
0
1
0
1
U, V, W
U, V, W
A, B, Z
Input
Pins
A, B
U, V
U, V
Z
-
Encoder pulse
Encoder pulse
Encoder pulse
Encoder pulse
(ENCLK)
(ENCLK)
(ENCLK)
(ENCLK)
Count
fsys
fsys
fsys
fsys
TMPM370 19-22
Up/Down Counter Clear Conditions
Down
Down
Down
Down
Up
Up
Up
Up
Up
Up
Up
Up
[1] <ENCLR> is set to 1.
[2] counter=<RELOAD>
[1] <ENCLR> is set to 1.
[1] <ENCLR> is set to 1.
[2] counter=<RELOAD>
[3] Z trigger
[1] <ENCLR> is set to 1.
[1] <ENCLR> is set to 1.
[2] counter=16’hFFFF
[1] <ENCLR> is set to 1.
[1] <ENCLR> is set to 1.
[2] counter=0xFFFF
[1] <ENCLR> is set to 1.
[1] <ENCLR> is set to 1.
[2] counter=0xFFFFFF
[3]
(ENCLK)
[1] <ENCLR> is set to 1.
[2] counter=0xFFFFFF
[3] counter=<EN0INT>
[1] <ENCLR> is set to 1.
[2] counter=0xFFFFFF
[3] counter=<EN0INT>
[4] Z trigger
Encoder
pulse
-
[1] counter=0x0000
-
[1] counter=0x0000
-
[1] counter=0x0000
-
[1] counter=0x0000
Counter Reload
Conditions
Encoder Input Circuit
0x0000 thru.
0x0000 thru.
<RELOAD>
TMPM370
0xFFFFFF
0xFFFFFF
0x000000
0x000000
Counter
(Reload
0xFFFF
Range
Value)
thru.
thru.