TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 150
TMPM370FYFG
Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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TBnCR
(0x4001_0xx8)
9.4.1.3
<TBWBF>:Controls the enabling/disabling of double buffering.
<CSSELn>: Selects how the timer starts counting.
<TRGSELn>: Selects the active edge of the external trigger signal.
<I2TBn>:Controls the clock keep/ stop operation during the IDLE mode.
(Note1) TBnCR resister must not be changed during Timer operation TBnRUN<TERUN>=1”.
(Note2) When the external trigger start is used (<CSSELn>=”1”), select <CSSELn> and
bit Symbol
Read/Write
After reset
Read/Write
Read/Write
Read/Write
bit Symbol
bit Symbol
bit Symbol
After reset
After reset
After reset
Function
TMRB control register (channels 0 through 7)
0: Select software for timer count start.
1: Select external trigger for timer count start.
<TRGSELn> before the setting of <TBnRUN>=<TBnPRUN>=”1”.
0: Select rising edge of external trigger.
1: Select falling edge of external trigger.
0: Stop the clock.
1: Keep clock operation during IDLE mode.
0: Disable Double Buffer.
1: Enable Double Buffer.
Double
Buffer
0: Disabled
1: Enabled
TBnWBF
R/W
31
23
15
R
R
R
7
0
0
0
0
Write “0”.
R/W
30
22
14
R
R
R
6
0
0
0
0
TMRBn control register (n=0 to 7)
Write “0”.
R/W
29
21
13
TMPM370 9-7
R
R
R
5
0
0
0
0
“0” is read. IDLE
28
20
12
R
R
R
4
R
0
0
0
0
0:Stop
1:Operation
I2TBn
R/W
27
19
11
R
R
R
3
0
0
0
0
“0” is read. External
16-bit Timer/Event Counters
26
18
10
R
R
R
2
R
0
0
0
0
Trigger
select
0: Rising
1: Falling
TRGSELn
edge
edge
R/W
25
17
R
R
9
R
1
0
0
0
0
Counter
Start select
0: Software
1: External
CSSELn
start
trigger
R/W
24
16
TMPM370
R
R
8
R
0
0
0
0
0
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