TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 46

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(1) Execution after returning from an ISR
(2) Exception exit sequence
the highest priority pending exception, the CPU returns to the last stacked ISR.
If there are no pending or stacked exceptions, the CPU returns to the previous program.
7.1.2.3
7.1.2.4
the user.
occur again upon return to normal program execution.
the currently executing ISR and services the newly detected exception.
priority than all stacked exceptions, the CPU returns to the ISR of the pending exception.
and entering another. This is called “tail-chaining”.
If there are no pending exceptions or if the highest priority stacked exception is higher priority than
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
When returning from an ISR, the CPU takes one of the following actions:
If a pending exception exists and there are no stacked exceptions or the pending exception has higher
When returning from an ISR, the CPU performs the following operations:
Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the SP.
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not
For details about interrupt handling, see “7.5 Interrupts”.
In this case, the CPU skips the pop of eight registers and push of eight registers when exiting one ISR
Tail-chaining
Returning to the last stacked ISR
Returning to the previous program
Pop eight registers
Executing an ISR
Exception exit
TMPM370 7-8
TMPM370
Interrupt