TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 422

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the address
specified by the 19th to 22nd bytes.
13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th
14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes.
to mth bytes together, drop the carries and take the two’s complement of the total sum.
Transmit this checksum value from the controller to the target board. The checksum
calculation is described in details in a later section “Checksum Calculation”.
If there was a receive error, the RAM Transfer routine sends back 18H (bit 3) and
returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this
case, the upper four bits of the acknowledge response are the same as those of the
previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface
mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the
carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case
of a checksum error, the RAM Transfer routine sends back 0x11 (bit 0) to the controller
and returns to the command wait state (i.e., the 3rd byte) again. When the above
checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (0x10) to the controller.
First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes.
TMPM370 20-30
Flash Memory Operation
TMPM370