EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 775

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
nRS
RDYnBSY
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
I/O
I/O
User Mode
PPA
PPA
Configuration
Scheme
Input
Output
Pin Type
Read strobe input. A low input directs the
device to drive the
DATA7
If the
should be tied high. In non-PPA schemes, it
functions as a user I/O during configuration,
which means it is tri-stated.
After PPA configuration,
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
Ready output. A high output indicates that the
target device is ready to accept another data
byte. A low output indicates that the target
device is busy and not ready to receive another
data byte.
In PPA configuration schemes, this pin drives
out high after power-up, before configuration
and after configuration before entering user-
mode. In non-PPA schemes, it functions as a
user I/O during configuration, which means it is
tri-stated.
After PPA configuration,
as a user I/O and the state of this pin depends
on the Dual-Purpose Pin settings.
Configuring Stratix & Stratix GX Devices
nRS
pin.
Stratix Device Handbook, Volume 2
pin is not used in PPA mode, it
Description
RDYnBSY
(Part 7 of 8)
RDYnBSY
nRS
is available as a
signal on the
is available
11–57