EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 330

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Enhanced PLLs
Figure 1–9. Low-Bandwidth PLL Lock Time
1–20
Stratix Device Handbook, Volume 2
Frequency (MHz)
125
160
155
150
145
140
135
130
120
0
finite range to customize the PLL characteristics for a particular
application. Applications that require clock switchover (such as TDMA,
frequency hopping wireless, and redundant clocking) can benefit from
the programmable bandwidth feature of the Stratix and Stratix GX PLLs.
The bandwidth and stability of such a system is determined by a number
of factors including the charge pump current, the loop filter resistor
value, the high-frequency capacitor value (in the loop filter), and the m-
counter value. You can use the Quartus II software to control these factors
and to set the bandwidth to the desired value within a given range.
You can set the bandwidth to the appropriate value to balance the need
for jitter filtering and lock time.
a low- and high-bandwidth PLL, respectively, as it locks onto the input
clock.
5
Lock Time = 8 μs
Time (μs)
Figures 1–9
10
and
1–10
show the output of
Altera Corporation
July 2005
15