EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 611
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 611 of 864
- Download datasheet (11Mb)
Figure 7–19. 2-Tap 18-Bit Complex FIR Filter Implementation
Altera Corporation
September 2004
x
x
x
h
h
x
h
h
imag1
imag2
real1
real2
real1
imag1
real2
imag2
f
DSP block
DSP block
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
For more information on the different modes of the DSP blocks, see the
DSP Blocks in Stratix & Stratix GX Devices chapter.
Figure 7–19
18-bit inputs. The real and the complex outputs of the DSP blocks are
added externally to generate the overall real and imaginary output. As in
the case of basic, TDM, or polyphase FIR filters, the coefficients may be
loaded in series or parallel.
out
out
out
out
Configured as a subtractor
Configured as a subtractor
Configured as a adder
Configured as a adder
imag1
imag2
real1
real2
shows an example of a 2-tap complex FIR filter design with
= x
= x
= x
= x
real1 *
real2 *
real1 *
real2 *
h
h
h
h
imag1
imag2
real1
real2
- x
- x
+ x
+ x
imag1 *
imag2 *
imag1 *
imag2 *
h
h
h
h
imag1
imag2
real1
real2
Stratix Device Handbook, Volume 2
Overall imaginary output
Overall real output
7–33
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