EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 215
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 215 of 864
- Download datasheet (11Mb)
Altera Corporation
January 2006
Table 4–54
clock networks.
Notes to
(1)
(2)
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
XZPLL
ZXPLL
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2
of 2)
Table 4–54. Stratix Global Clock External I/O Timing Parameters
(2)
Symbol
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
Table
Table
shows the external I/O timing parameters when using global
Setup time for input or bidirectional pin using IOE input register with
global clock fed by
Hold time for input or bidirectional pin using IOE input register with
global clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
(1),
4–53:
4–54:
(2)
CLK
CLK
pin
pin
Parameter
Parameter
Stratix Device Handbook, Volume 1
CLK
DC & Switching Characteristics
pin
Notes
(1),
4–35
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