EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 351

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
RCLK[12..15] are in the bottom-right quadrant. The regional clock
networks only pertain to the quadrant they drive into. The regional clock
networks provide the lowest clock delay and skew for logic contained
within a single quadrant. RCLK clock networks cannot be driven by
internal logic. The CLK clock pins symmetrically drive the RCLK networks
within a particular quadrant, as shown in
and
Figure 1–20. Regional Clocks
Clock Input Connections
Two CLK pins drive each enhanced PLL. You can use either one or both
pins for clock switchover inputs into the PLL. Either pin can be the
primary clock source for clock switchover, which is controlled in the
Quartus II software. Enhanced PLLs 5 and 6 also have feedback input
pins as shown in
RCLK[1..0]
RCLK[4..5]
1–22
CLK[3..0]
for RCLK connections from PLLs and CLK pins.
Table
General-Purpose PLLs in Stratix & Stratix GX Devices
1–14.
RCLK[6..7]
RCLK[2..3]
CLK[7..4]
RCLK[12..13]
RCLK[11..10]
CLK[15..12]
Stratix Device Handbook, Volume 2
Figure
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
1–20. See
CLK[11..8]
Figures 1–21
RCLK[14..15]
RCLK[9..8]
1–41