EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 752

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Configuration Schemes
Figure 11–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
11–34
Stratix Device Handbook, Volume 2
CONF_DONE
Upon power-up, nSTATUS is held low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or
Stratix GX device.
Device I/O pins are in user mode.
RDYnBSY
nSTATUS
Figure
DATA[7..0]
INIT_DONE
nCONFIG
nWS
nCS
User I/Os
CS
(
(
(
(
(
(
11–18:
1)
2)
3)
3)
3)
3)
t
t
CF2CD
t
CF2ST0
CFG
t
STATUS
t
CF2ST1
PPA Configuration Timing
Figure 11–18
for PPA configuration.
t
CF2WS
High-Z
t
CSSU
t
DSU
Byte 0
t
DH
shows the Stratix and Stratix GX device timing waveforms
t
WS2B
t
WSP
Byte 1
t
RDY2WS
Byte n Ð 1
t
CSSU
t
CSH
t
BUSY
Byte n
Altera Corporation
t
July 2005
CD2UM
(
(
(
(
(
4)
4)
4)
4)
4)