EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 627
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 627 of 864
- Download datasheet (11Mb)
Figure 7–28. Block Diagram on Implementation of 3
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
RAM blocks. The 9-bit signed filter coefficients feed directly into the filter
block. As the data is shifted out from the RAM blocks, the multiplexer
block checks for edge pixels and uses the free boundary condition.
Figure 7–28
The 3
parallel using two DSP blocks. One DSP block can implement eight of
these multipliers. The second DSP block implements the ninth multiplier.
The first DSP block is in the four-multipliers adder mode, and the second
is in simple multiplier mode. In addition to the two DSP blocks, an
external adder is required to sum the output of all nine multipliers.
Figure 7–29
3 filter block implements the nine multiply-add operations in
shows a top-level diagram of the design.
shows this implementation.
3 Convolutional Filter for an 8
Stratix Device Handbook, Volume 2
8 Pixel Input Image
7–49
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