EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 522

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Board Design Consideration
Figure 5–39. Differential SSTL-2 Class II Termination
Board Design
Consideration
5–50
Stratix Device Handbook, Volume 2
Transmitter
Differential
25 Ω
25 Ω
50 Ω
This section is a brief explanation of how to get the optimal performance
from the Stratix high-speed I/O block and ensure first-time success in
implementing a functional design with optimal signal quality. For more
information on detailed board layout recommendation and I/O pin
terminations see AN 224: High-Speed Board Layout Guidelines.
You must consider the critical issues of controlled impedance of traces
and connectors, differential routing, and termination techniques to get
the best performance from the IC. For more information, use this chapter
and the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1.
The Stratix high-speed module generates signals that travel over the
media at frequencies as high as 840 Mbps. Board designers should use the
following general guidelines:
■
■
■
■
■
■
■
V
TT
= 1.25 V
Baseboard designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Place external reference resistors as close to receiver input pins as
possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HS-3 connectors for
backplane designs. High-performance connectors are provided by
Teradyne Corp (www.teradyne.com) or Tyco International Ltd.
(www.tyco.com).
Design backplane and card traces so that trace impedance matches
the connector’s and/or the termination’s impedance.
Keep equal number of vias for both signal traces.
50 Ω
V
TT
= 1.25 V
Z
Z
0
0
= 50 Ω
= 50 Ω
50 Ω
V
TT
= 1.25 V
50 Ω
V
TT
= 1.25 V
Altera Corporation
Differential
Receiver
July 2005