EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 388
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 388 of 864
- Download datasheet (11Mb)
Clock Modes
Figure 2–11. Input/Output Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
(3)
(4)
2–20
Stratix Device Handbook, Volume 2
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
For more information on the MultiTrack™ interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
wren
rden
Figure
8 LAB Row
Clocks
8
2–11:
All registers shown have asynchronous clear ports, except when using
the M-RAM. M-RAM blocks have asynchronous clear ports on their
output registers only.
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Notes
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
(1), (2), (3),
512 ´ 8
D
ENA
(4)
Q
Altera Corporation
To MultiTrack
Interconnect
July 2005
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