EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 503
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 503 of 864
- Download datasheet (11Mb)
Figure 5–23. Bit Orientation in the Quartus II Software
Figure 5–24. Bit Order for One Channel of Differential Data
Altera Corporation
July 2005
high-frequency clock
Example: Sending the Data 10010110
Data in/
Data out
Data in/
Data out
inclock/outclock
inclock/outclock
data in
Previous Cycle
Previous Cycle
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies.
channel operating in
significant bits (MSBs) and least significant bits (LSBs) after
deserialization, as listed in
n-1
n-0
MSB
MSB
D7
1
MSB
9
D6
Figure 5–24
0
High-Speed Differential I/O Interfaces in Stratix Devices
8
×
D5
0
8 mode. Similar positioning exists for the most
7
Current Cycle
Current Cycle
D4
1
Table
6
shows the data bit orientation for a receiver
D3
0
10 LVDS Bits
5–5.
5
D2
1
4
Stratix Device Handbook, Volume 2
D1
1
3
LSB
LSB
D0
0
2
1
Next Cycle
Next Cycle
LSB
0
5–31
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