EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 573
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 573 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
cleared for the next accumulation cycle, and you can use an external latch
to preserve the signal. You can use the addnsub[1..0] signals to
perform accumulation or subtraction dynamically.
1
Two-Multiplier Adder Mode
The two-multiplier adder mode uses the adder/output block to add or
subtract the outputs of the multiplier block, which is useful for
applications such as FFT functions and complex FIR filters. Additionally,
in this mode, the DSP block outputs two sums or differences for
multipliers up to 18 bits, or 4 sums or differences for 9-bit or smaller
multipliers. A single DSP block can implement one 18
multiplier or two 9
A complex multiplication can be written as:
In this mode, a single DSP block calculates the real part (a
one adder/subtractor/accumulator and the imaginary part (a
using another adder/subtractor/accumulator for data up to 18 bits.
Figure 6–13
to 9 bits, the DSP block can perform two complex multiplications using
four one-level adders. Resources outside of the DSP block route each
input to the two multiplier inputs.
1
(a + jb)
If you want to use DSP blocks and your design only has an
accumulator, you can use a multiply by one followed by an
accumulator to force the software to implement the logic in the
DSP block.
You can only use the adder block if it follows multiplication
operations.
shows an 18-bit complex multiplication. For data widths up
(c + jd) = (a
9-bit complex multipliers.
c – b
DSP Blocks in Stratix & Stratix GX Devices
d) + j
Stratix Device Handbook, Volume 2
(a
d + b
c)
18-bit complex
c – b
d + b
d) using
6–23
c)
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