EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 438
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 438 of 864
- Download datasheet (11Mb)
Stratix & Stratix GX I/O Standards
4–10
Stratix Device Handbook, Volume 2
Figure 4–7. SSTL-3 Class I Termination
Figure 4–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
– 0.3 V V
V
Figures 4–9
and output levels.
Figure 4–9. SSTL-2 Class I Termination
TT
to which the series and termination resistors are connected (see
I
Output Buffer
and 4–10). Stratix and Stratix GX devices support both input
Output Buffer
V
Output Buffer
CCIO
+ 0.3 V. SSTL-2 requires a 1.25-V V
25 Ω
25 Ω
25 Ω
V
TT
= 1.5 V
V
V
REF
REF
50 Ω
V
Z = 50 Ω
Z = 50 Ω
REF
= 1.25 V
Z = 50 Ω
= 1.5 V
= 1.5 V
V
V
TT
TT
V
TT
= 1.5 V
= 1.25 V
= 1.5 V
50 Ω
50 Ω
50 Ω
Input Buffer
Input Buffer
REF
Input Buffer
Altera Corporation
and a 1.25-V
June 2006
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