EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 471

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Altera Corporation
June 2006
Accelerated Graphics Port Interface Specification 2.0, Intel
Corporation.
Stub Series Terminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest
Group.
UTOPIA Level 4, AF-PHY-0144.001, ATM Technical Committee.
POS-PHY Level 4: SPI-4, OIF-SPI4-02.0, Optical Internetworking
Forum.
POS-PHY Level 4: SFI-4, OIF-SFI4-01.0, Optical Internetworking
Forum.
Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
4–43

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