EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 630
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Discrete Cosine Transform (DCT)
Discrete Cosine
Transform (DCT)
7–52
Stratix Device Handbook, Volume 2
Convolution Implementation Results
Table 7–17
Figure
The design requires the input to be an 8
and 9-bit filter coefficient width. The output is an image of the same size.
Convolution Design Example
Download the 3
example from the Design Examples section of the Altera web site at
www.altera.com.
The discrete cosine transform (DCT) is widely used in video and audio
compression, for example in JPEG, MPEG video, and MPEG audio. It is a
form of transform coding, which is the preferred method for compression
techniques. Images tend to compact their energy in the frequency domain
making compression in the frequency domain much more effective. This
is an important element in compressing data, where the goal is to have a
high data compression rate without significant degradation in the image
quality.
DCT Background
Similar to the discrete fourier transform (DFT), the DCT is a function that
maps the input signal or image from the spatial to the frequency domain.
It transforms the input into a linear combination of weighted basis
functions. These basis functions are the frequency components of the
input data.
Part
Utilization
Performance
Latency
Table 7–17. 3
7–28.
shows the results of the 3
3 2-D Convolution Filter Implementation Results
EP1S10F780
Lcell: 372/10570 (3%)
DSP block 9-bit elements: 9/48 (18%)
Memory bits: 768/920448 (<1%)
226 MHz
15 clock cycles
3 2-D Convolutional Filter (two_d_fir.zip) design
3 2-D FIR filter implementation in
8 image, with 8-bit input data
Altera Corporation
September 2004
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