EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 457
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 457 of 864
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Figure 4–20. Differential Termination
Altera Corporation
June 2006
Transmitter
Differential
For more information on termination for voltage-referenced I/O
standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device
Handbook, Volume 2.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix and Stratix GX
devices provide an optional differential termination on-chip resistor
when using LVDS.
See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for
more information on differential I/O standards and their interfaces.
For differential I/O standards, I/O banks support differential
termination when V
Differential Termination (R
Stratix devices support differential on-chip termination for source-
synchronous LVDS signaling. The differential termination resistors are
adjacent to the differential input buffers on the device. This placement
eliminates stub effects, improving the signal integrity of the serial link.
Using differential on-chip termination resistors also saves board space.
Figure 4–20
Stratix GX devices.
shows the differential termination connections for Stratix and
Selectable I/O Standards in Stratix & Stratix GX Devices
CCIO
Z 0
Z 0
equals 3.3 V.
D
)
Stratix Device Handbook, Volume 2
Differential On-Chip Termination
Receiver Buffer with
R
D
Stratix LVDS
4–29
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