EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 504
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 504 of 864
- Download datasheet (11Mb)
Source-Synchronous Timing Budget
5–32
Stratix Device Handbook, Volume 2
t
f
t
C
HSCLK
RISE
Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2)
High-Speed Timing Specification
Table 5–5
18 differential channels. However, the MSB and LSB are increased with
the number of channels used in a system.
Timing Definition
The specifications used to define high-speed timing are described in
Table
Table 5–5. LVDS Bit Naming
Receiver Data Channel
5–6.
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
shows the conventions for differential bit naming for
Number
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
MSB Position
Terminology
Internal 8-Bit Parallel Data
103
111
119
127
135
143
15
23
31
39
47
55
63
71
79
87
95
7
Altera Corporation
LSB Position
104
112
120
128
136
16
24
32
40
48
56
64
72
80
88
96
0
8
July 2005
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